The invention relates to a self-calibrating digital-to-analog converter that requires a less limited range of its digital input signal to avoid distortion of its analog output than is the case for prior self-calibrating digital-to-analog converters. The invention also relates to such a self-calibrating digital-to-analog converter which does not skew its valid digital input range as a result of digital self-calibration to accomplish an offset correction, or as a result of switching from a self-calibrating mode to a normal operating mode.
U.S. Pat. No. 5,087,914 (Sooch et al) discloses the closest prior art presently known to the inventor. FIG. 1 of U.S. Pat. No. 5,087,914 shows a digital-to-analog conversion system in which a digital input 18 is converted to an analog output on conductor 34. The system includes a digital section 10 that performs two main functions, the first of which is to convert an 18-bit digital input word on bus 18 to a 1-bit digital data stream that appears on a single conductor 20. It accomplishes this mainly by an oversampling system that includes an interpolation filter and sample/hold circuitry in block 14, and applies that information in parallel form to the digital inputs of a delta-sigma modulator 16. Delta-sigma modulator 16 functions as a "quantizer" that converts the parallel digital data input to it into a 1-bit digital data stream containing essentially the same digital information.
The second function performed by digital section 10 of U.S. Pat. No. 5,087,914 is to perform a digital self-calibration to adjust for an analog "offset" voltage that, because of inaccuracies in the circuit components, would otherwise appear on analog output conductor 34 if all eighteen bits of the digital input on BUS 18 were set to logical "0"s. To accomplish the self-calibration, the system of U.S. Pat. No. 5,087,914 converts the analog offset voltage to a digital number which is stored in offset register 19 and then is added by means of adder 24 to the digital output produced by the interpolation filter and sample/hold circuitry 14. The addition of adder 24 is performed before or ahead of the delta-sigma modulator 16. The digital offset correction provides a more accurate parallel data input to delta-sigma modulator 16. Therefore, any digital input word applied to input conductors 18 will be converted to an accurate analog output voltage, with the offset error having been cancelled by offset register 26 and parallel adder 24.
Analog section 12 of U.S. Pat. No. 5,087,914 includes a 1-bit digital-to-analog converter 21 followed by an analog filter 22 and an output operational amplifier 28. During a self-calibration operation, operational amplifier 28 amplifies the output of analog filter 22 and feeds it back via a comparator 28 to a calibration control circuit 40 which computes an offset value by a successive approximation technique and loads it into offset register 26. Meanwhile, isolation operational amplifier 28 isolates the analog output 34 from the output of output operational amplifier 28 during the entire self-calibration procedure and also closes switch 44 to thereby clamp analog output 34 to ground.
A problem with performing the self-calibration ahead of the delta-sigma modulator as disclosed in U.S. Pat. No. 5,087,914 is that adding a digital offset correction number to the digital input word before it is applied as an input to the delta-sigma modulator skews the valid digital input signal range of the delta-sigma modulator by the amount of the digital offset correction. That can result in "clipping" of digital bits within the delta-sigma modulator at the end of the input signal range which is diminished by the amount of the digital offset correction. That makes it necessary to add one or more bits to the length of the digital input word if it is desired to avoid distortion of the analog output of the digital-to-analog converter that is caused by diminishing one end of the valid digital input range by the amount of the digital offset correction. Thus, the self-calibration technique described in U.S. Pat. No. 5,087,914 either diminishes the digital input range or requires addition of one or more bits to the length of the digital input word; the latter increases the complexity and amount of chip area required for an integrated circuit implementation of the digital-to-analog converter 1.
Another problem of the self-calibration scheme disclosed in U.S. Pat. No. 5,087,914 is that the analog output terminal is clamped to the ground reference voltage level by switch 44 during each self-calibration operation. That ground level may be an "invalid" level with respect to an external utilization system that receives the output signal of the digital-to-analog converter, and therefore may be very undesirable in the utilization system because it may necessitate disabling the entire utilization system during self-calibration of the digital-to-analog converter of the '914 patent. In any case, additional time then must be allowed for the utilization system to recover when the analog output on conductor 34 is unclamped after the self-calibration procedure is complete. Thus, there is a need for a self-calibrated digital-to-analog converter which does not limit the digital input range or clamp the output during the self-calibration operation.
Another problem with the self-calibration scheme disclosed in U.S. Pat. No. 5,087,914 is that since the feedback resistor 36 is clamped to ground during the self-calibration operation, it can not also be used to establish the gain of amplifier 28 during self-calibration. Therefore, the system disclosed in U.S. Pat. No. 5,087,914 would not be expected to provide self-calibration of the gain of the digital-to-analog converter.